The present invention relates to a method of fabricating a capacitor for semiconductor memory devices, more particularly to a method of fabricating a capacitor for semiconductor memory devices employing a Ta2O5 layer as a dielectric layer.
As the number of memory cells for consisting DRAM semiconductor device has been increased recently, occupation dimension of the memory cells is gradually decreased. Meanwhile, capacitors formed in the respective memory cells require a sufficient capacitance for precise reading out of storage data. Accordingly, capacitors in the current DRAM semiconductor devices are required to occupy small dimension as well as to provide a greater capacitance. The capacitance of a capacitor can be increased by using an insulator of high dielectric constant as a dielectric layer, or by enlarging the dimension of a lower electrode. In a highly integrated DRAM semiconductor device, Ta2O5 having a higher dielectric constant than that of the nitride-oxide(NO) is presently used as a dielectric, thereby forming the lower electrode a 3-Dimentional structure.
FIG. 1 is a cross-sectional view for showing a capacitor for conventional semiconductor memory devices. Referring to FIG. 1, a gate electrode 13 including a gate insulating layer 12 at a lower portion thereof is formed according to a known technique on a semiconductor substrate 10 in which a field oxide layer 11 is formed at a selected portion. A junction region 14 is formed on the semiconductor substrate 10 of both sides of the gate electrode 13 thereby forming an MOS transistor. A first interlevel insulating layer 16 and a second interlevel insulating layer 18 are formed on the semiconductor substrate 10 in which the MOS transistor is formed. A storage node contact hole h is formed inside the first and the second interlevel insulating layers 16, 18 so that the junction region 14 is exposed. A cylinder type lower electrode 20 is formed according to a known method, inside the storage node contact hole h so as to be in contact with the exposed junction region 14. A HSG(hemi-spherical grain) layer 21 is formed on a surface of the lower electrode 20 so as to more increase surface dimension of the lower electrode 20. A surface of the lower electrode 20 including the HSG layer 21 is cleaned. A Ta2O5 layer 23 is deposited on an upper portion of the lower electrode 20 and on the second interlevel insulating layer 18. The Ta2O5 layer 23 can be formed by the CVD(chemical vapor deposition) method due to a reaction between a tantalum containing precursor and O2. At this time, as for the conventional precursors, there have been used Ta(OC2H5) [tantalum pentaethoxide], TaCl2(OC2H5)2C5H7O2[dichloro-diethoxy-acetylacetonate], Ta(N(CH3)2)5[penta-dimethyl-amino-tantalum], Ta(DMP)4Cl[tantalum chloro-tetradipivaloymethane], and Ta(OCH3)5[tantalum pentamethoxide]. Afterward, the Ta2O5 layer 23 in the amorphous state is became the crystalline state by a predetermined thermal process. Then, an upper electrode 25 is formed on the Ta2O5 layer 23 according to a known method.
However, since the conventional Ta2O5 layer is formed by the reaction between the precursor having carbon components and oxygen, there are remained reaction by-products such as carbon atoms, carbon compounds (C, CH4, C2H4) and H2O in the Ta2O5 layer. Those reaction by-products incur leakage current and degrade the dielectric strength of the Ta2O5 layer.
In the conventional method, thermal processes at low and high temperatures are performed to remove those reaction by-products after the Ta2O5 layer is formed.
The thermal processes of low and high temperatures can remove the by-products, however this method increases manufacturing steps.
Accordingly, object of the present invention is to provide a method of manufacturing a capacitor for semiconductor memory devices capable of lowering leakage current, obtaining great capacitance and reducing manufacturing steps.
To accomplish the foregoing object, the method according to an embodiment of the present invention includes the steps of: forming a lower electrode on the semiconductor substrate; forming a Ta2O5 layer with a tantalum-based carbon-free precursor on the lower electrode; and forming an upper electrode on the Ta2O5 layer.
According to another embodiment of the present invention, the method includes the steps of: forming a lower electrode on the semiconductor substrate; forming a Ta2O5 layer with TaF5 solid source as a precursor on the lower electrode; and forming an upper electrode on the Ta2O5 layer.
According to still another embodiment of the present invention, the method includes the steps of: forming a lower electrode on the semiconductor substrate; forming a Ta2O5 layer with TaCl5 solid source as a precursor on the lower electrode; and forming an upper electrode on the Ta2O5 layer.
Herein, the Ta2O5 layer is formed by vaporizing the precursor and injecting into a chamber for generating the Ta2O5 layer, and simultaneously injecting hydrogen and oxygen gases and reacting according to a chemical vapor reaction of the vaporized precursor, hydrogen gas and oxygen gas.